Cache memory is used in computer systems in order to increase performance by alleviating the need for a processor to fetch instructions from main system memory sources, such as dynamic random-access memory (DRAM). DRAM and other main memory sources may require longer access times due to the paging and memory cell access speed of such memory sources, which can cause the processor to incur wait-states and degrade computer system performance.
Cache memory, on the other hand, provides the processor with a way to fetch instructions quickly without incurring the wait-states associated with main memory sources, such as DRAM. Using cache memory improves computer system performance by making commonly-used instructions available to the processor in a memory architecture that does not require paging cycles, that uses a relatively fast-access memory cell, and that places the cache memory in close proximity to the processor's local bus in order to reduce physical delay associated with bus structures.
Similarly, instruction caches can also be used in high-performance microprocessor to decrease the average instruction fetch latency. In order to further decrease fetch latency, instructions may be cached in decoded, or “micro-op” (uop), format. Advantageously, caching instructions in uop format can decrease instruction decode logic within the microprocessor, because only instructions fetched as a result of a cache miss need be decoded.
Typically, one uop is able to be stored in each cache memory entry, as illustrated in FIG. 1, thereby limiting the number of instructions that may be cached at once within a cache memory. Furthermore, some instructions contain more than one uop, resulting in more than one cache entry being used to store a single instruction.